Some Xilinx Zynq (or Altera Cyclone V SoC) applications require a huge amount of data to be processed by an FPGA accelerator and then sent back to the ARM processor immediately. The goal of this demonstration is to show how simple it can be to write an application based on the RSoC Framework for Zynq. The application consists of FPGA and processor parts. The FPGA part is used to forward data coming from processor back to the same processor through RAM (loopback). The processor controls sending of data. A scheme of the solution is depicted in the Figure.
Asymmetric MultiProcessing (AMP) is vital for isolating safety or real-time critical processing in embedded applications. The RSoC Framework supports asymmetric multiprocessing on dualcores such as ARM Cortex-A9. One core hosts classical Linux with non-critical application processing whereas the other core hosts the critical processing running either without OS support (bare metal) or with FreeRTOS support. A simplified scheme of the RSoC Framework support of AMP is depicted in the Figure.
The task was to develop embedded solution for online encryption of a packet stream. The solution was built around Xilinx Zynq. The critical encryption task was implemented in the FPGA logic whereas the ARM in the Zynq was utilized to deal with more complex but not that time-critical tasks. A simplified scheme of the solution is depicted in the Figure.
The solution performs data encryption and transmits the data over the network to a remote host. The encryption is offloaded into the FPGA part. This reduces the load of CPUs.
The Linux running in the ARM serves as a streaming server delivering an encrypted video stream to connected clients. The streaming starts with an exchange of encryption keys. The data are transferred via RSoC Framework to the encryption engine implemented in FPGA. The encrypted data are transferred back and transmitted out over the Ethernet interface.
Video processing applications often require hardware acceleration to reduce processor load and power consumption. Xilinx Zynq consist of the ARM Cortex-A9 and the FPGA logic for hardware acceleration. Therefore it is a perfect platform to implement accelerated embedded video processing solution. In this demonstration the time-critical task of video noise filtering (by 3×3 median filter) is implemented:
as a standard program for ARM processor,
using intrinsic functions for ARM NEON and
as an acceleration engine in the FPGA logic.
In all cases, ARM processor is utilized to control the video stream. The user application running in Linux loads a video file from the local flash storage. This noisy video stream is processed by (1) ARM processor, (2) ARM NEON engine or (3) sent to the engine implemented in FPGA.
A simplified scheme of the solution is depicted in the Figure:
The RSoC Framework is utilized to achieve high throughput between ARM and FPGA logic and to simplify design process. There is no need for interconnections, DMA engine instantiation or driver development with use of RSoC Framework.
The processing (1,2 or 3) depends on the external button and it is also indicated on ZedBoard’s integrated OLED display. External button is handled by GPIO core (Xilinx XPS General Purpose IO). The GPIO can be connected either to RSoC Bridge or to the ARM directly. If the button is pushed, an interrupt is triggered to ARM to set up one of three types of processing or just send unfiltered video to the output. The video stream is forwarded to HDMI controller core which is implemented in the FPGA logic and displays the video on the monitor. Therefore it is possible to demonstrate the speed of image processing in three different implementations. You can see how this demo works at this YouTube video:
This video processing application has been prototyped rapidly with the RSoC Framework. You can downloadapplication sources. Or you can also download all binaries needed to run video demonstration application on the ZedBoard. Corresponding application note is also available for download.
The task was to develop embedded solution for remote network wire tapping of 1Gbps links. The solution was built around Xilinx Zynq. The critical and simple tasks were implemented in the FPGA logic whereas the ARM in the Zynq was utilized to deal with more complex but not that time-critical tasks. A simplified scheme of the solution is depicted in the Figure.
The Linux running in the ARM listens on the management interface for an SSH connection. The SSH connection is utilized to configure filtering rules remotely. The filtering rules are uploaded into the Packet Filter utilizing RSoC Driver, RSoC Bridge. The AXI-Lite bus is utilized to transfer configuration data to the Packet Filter.
Meanwhile the packets are received at the dedicated Ethernet Interface at the full line rate. The EMAC core (e.g. Tri-mode Ethernet Media Access Controller – provided by Xilinx) buffers the incoming packets and transfers the received packets via AXI-Stream interface to the Packet Filter. The Packet Filter filters out packets that are not of the interest and only the packets that match any filtering rule pass via AXI-Stream to the RSoC Bridge, RSoC driver to the user application.
The user application has already established a TCP connection and sends the received packets to the remote packet collector.