What is RSoC

RSoC (Reconfigurable System-on-Chip) is a chip consisting of a powerful processor (e.g. ARM Cortex-A9 MPCore) and a reconfigurable area (Programmable Logic – FPGA). Such platforms allows the HW/SW co-design or acceleration of already existing applications. Examples are Xilinx Zynq All Programmable SoC or Altera SoC.

What is RSoC Framework

RSoC (Reconfigurable System-on-Chip) Framework is a solution for development of applications on platforms consisting of processors and an FPGA on a single die. The RSoC Framework provides a support for interconnection of applications running on the processors with their complements hosted in the FPGA transparently. The RSoC Framework can run either in the RSoC or in the soft FPGA processor core, such as Xilinx MicroBlaze Soft Processor Core, Altera NIOS II Processor and many others.

Why RSoC Framework

The RSoC Framework brings several advantages. The Framework

  • speeds up the development on the embedded platforms which results in shorter time to market delivery
  • mitigates the risk of errors in the critical communication interface
  • is easy to use, customizable, generic and scalable
  • is platform independent, thus easily portable on any RSoC platform
  • supports leading development tools

RSoC Framework Architecture

The Framework consists of an RSoC Bridge — an IP core that addresses the FPGA specific issues — and of an RSoC Driver — a software component (Linux drivers) covering the communication with the hardware accelerated application modules (called accelerators) in the FPGA.

rsoc-overview

  • RSoC Bridge consists of address decoders, DMA controllers (own one or other vendors are possible), bus systems and software integration. The core is highly configurable according to the number of accelerators, requirements on the internal data widths, accelerators to physical channel mappings, etc.

  • RSoC Driver recognizes the RSoC Bridge configuration and provides a software interface to access the accelerators. The software applications utilize the Driver to exchange data with the accelerators or to configure the accelerators.

RSoC Framework Throughput

In this section, the throughput of DMA from Linux userspace (using standard calls read(3), write(3), poll(3)) is shown. These numbers relevant for real applications measured with RSoC Framework on both Xilinx Zynq and Altera SoCFPGA. All measurements are done on 100 MHz via 64 bit data bus with descriptors prefetch turned off.

Platform Description Buffers Throughtput
Xilinx Zynq RX only I/O 128 * 4 kB 165 MB/s
Xilinx Zynq TX only I/O 128 * 4 kB 208 MB/s
Xilinx Zynq RX/TX loopback I/O 128 * 4 kB / 128 * 4 kB 100 MB/s
Altera SoCFPGA RX only I/O 128 * 4 kB 150 MB/s
Altera SoCFPGA TX only I/O 128 * 4 kB 129 MB/s
Altera SoCFPGA RX/TX loopback I/O 128 * 4 kB / 128 * 4 kB 172 MB/s

For faster transfers, a zero-copy approach can be used to reduce number of context-switchs. We are able to measure the following numbers with RSoC Framework on Xilinx Zynq.

Description Buffer size Throughtput
RX only I/O (explicit cache flush) 4 kB 238 MB/s
RX only I/O (explicit cache flush) 16 kB 251 MB/s
RX only I/O (caches off) 4 kB 426 MB/s
RX only I/O (caches off) 16 kB 546 MB/s

Note that accessing data in cache-coherent memory (caches off) is slow, however, it increases the raw throughput. This approach can be used when only a small part of the transferred data is read.

You can find out more in our RSoC Framework product brief.
Or download RSoC Framework leaflet which summarizes RSoC framework features.
Please contact us for more information.