New DMA engines under the hood

We were quiet for some time while working on new cool DMA backends for the RSoC Framework. As the general principle of the RSoC Framework promises, it provides a vendor independent stable interfaces for hardware accelerators and the related software. Accelerators can be quickly connected via the simple AXI-Stream buses and the software utilizes the well-known write(2), read(2) system calls (and more).

ARM PL330 DMA and Super DMA as new backends of the RSoC Framework

New DMA backends for RSoC Framework

However, under the hood, we can run different units the moves data between the FPGA and CPU (well, the memory). Until recently, we supported just a single DMA for both FPGA platforms, Xilinx Zynq and Altera SoC FPGA. But this is changing…

There are two new DMA engines inside the RSoC Framework:

  1. slower but with a very low resource consumption (utilizing the on-chip ARM PL330 DMA)
  2. very fast and low latency DMA (Super DMA)

Same interfaces, different performance, and different resource consumption.

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