The task was to develop embedded solution for remote network wire tapping of 1Gbps links. The solution was built around Xilinx Zynq. The critical and simple tasks were implemented in the FPGA logic whereas the ARM in the Zynq was utilized to deal with more complex but not that time-critical tasks. A simplified scheme of the solution is depicted in the Figure.
The Linux running in the ARM listens on the management interface for an SSH connection. The SSH connection is utilized to configure filtering rules remotely. The filtering rules are uploaded into the Packet Filter utilizing RSoC Driver, RSoC Bridge. The AXI-Lite bus is utilized to transfer configuration data to the Packet Filter.
Meanwhile the packets are received at the dedicated Ethernet Interface at the full line rate. The EMAC core (e.g. Tri-mode Ethernet Media Access Controller – provided by Xilinx) buffers the incoming packets and transfers the received packets via AXI-Stream interface to the Packet Filter. The Packet Filter filters out packets that are not of the interest and only the packets that match any filtering rule pass via AXI-Stream to the RSoC Bridge, RSoC driver to the user application.
The user application has already established a TCP connection and sends the received packets to the remote packet collector.